High-frequency chip packages

ABSTRACT

A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit board so as to provide enhanced thermal conductivity to the circuit board and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier. A module includes two circuits and an enclosure with a medial wall between the circuits to provide electromagnetic shielding between the circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of International Application No.PCT/US02/27509, filed Aug. 28, 2002, designating the United States. Saidinternational application claims the benefit of U.S. Provisional PatentApplication No. 60/315,408 filed Aug. 28, 2001. Said internationalapplication is also a continuation-in-part of U.S. patent applicationSer. No. 10/210,160, filed Aug. 1, 2002, which application also claimsthe benefit of said U.S. Provisional Patent Application No. 60/315,408.The disclosure of all of the aforesaid applications are herebyincorporated by reference herein.

BACKGROUND OF THE INVENTION

The present application relates to the art of packaging microelectronicelements such as semiconductor chips.

Semiconductor chips or dies commonly are provided in packages whichfacilitate handling of the chip during manufacture and mounting of thechip on an external substrate such as a circuit board or other circuitpanel. For example, certain packaged semiconductor chips sold under theregistered trademark μBGA® by Tessera, Inc., assignee of the presentapplication, incorporate a dielectric element having terminals. Theterminals are connected to contacts on the die itself. In particularlypreferred arrangements, the connections between the terminals and thedie are formed by flexible leads and the dielectric element, itsmounting to the die or both are arranged so that the terminals remainmoveable with respect to the chip. For example, where the dielectricelement overlies a surface of the chip, a layer of a compliant materialmay be provided between the dielectric element and the chip. Thepackaged chip can be mounted to a circuit board or other underlyingcircuit panel by soldering or otherwise bonding the terminals on thedielectric element to contact pads on the circuit board. Because theterminals on the dielectric element can move relative to the chip, theassembly can compensate for differential thermal expansion andcontraction of the chip and the circuit board during thermal cycling inservice, in storage and during manufacturing processes.

Assemblies of this type are described, for example, in U.S. Pat. Nos.5,148,265; 5,148,266; and 5,679,977. In certain embodiments, the leadscan be formed partially or wholly as elongated metallic strips extendingfrom the terminals along the dielectric element. These strips can beconnected to the contacts on the chip by wire bonds, so that the wirebonds and strips cooperatively constitute composite leads. In otherembodiments, the strips themselves can be connected directly to theterminals. Certain methods of forming strip-like leads and connectingnumerous strip-like leads to numerous contacts on a die are described inU.S. Pat. Nos. 6,054,756; 5,915,752; 5,787,581; 5,536,909; 5,390,844;5,491,302; 5,821,609; and 6,081,035, the disclosures of which areincorporated by reference herein.

The aforementioned structures, in their preferred embodiments, providepackaged chips with numerous advantageous including the aforementionedability to compensate for differential thermal expansion and hence highreliability; compatibility with surface-mounting techniques forassembling components to a circuit board and the ability to accommodatenumerous connections to the chip in a compact assembly. Some of thesepackages occupy an area of the circuit board just slightly larger thanthe area of the chip itself. Certain preferred packages of this typeprovide short, strip-like leads which minimize self-inductance in theleads and hence provide good high-frequency signal propagation.Moreover, certain packages according to this design can provide goodheat dissipation from the chip. These packages have been widely adoptedfor semiconductor chips in numerous applications.

However, despite these advancements in the art, still furtherimprovement and optimization would be desirable. Chips used forgenerating or processing radio frequency (“RF”) signals, commonlyreferred to as “RF chips”, are used in numerous devices includingcellular telephones and wireless data communication devices. RF chipstypically generate substantial amounts of heat. Although RF chipstypically have only a moderate number of input/output connections, andhence require only a moderate number of connections to the circuitboard, these connections should be made with low-inductance leads havingcontrolled, predictable impendence at the frequencies handled by thechip. The packages for RF chips should be compact and economical.Moreover, it would be desirable to provide packages which areparticularly well suited to RF chips using the same production equipmentand techniques used with other package designs as, for example, theμBGA® chips.

SUMMARY OF THE INVENTION

One aspect of the present invention provides a semiconductor chipassembly. A semiconductor chip assembly according to this aspect of theinvention desirably includes a packaged semiconductor chip incorporatinga semiconductor die having a front surface, a rear surface and contactsexposed at the front surface. The packaged semiconductor chip alsoincludes a chip carrier having inner and outer surfaces. The innersurface of the chip carrier faces toward the front surface of the die.The chip carrier also has a plurality of terminals and a thermallyconductor, preferably formed from a metallic material, exposed at theouter surface of the chip carrier. The thermal conductor has arelatively large area, substantially larger than the area of eachindividual terminal. The thermal conductor may have an area of at least10 times, and desirably at least 20 times, the area of a singleterminal. The thermal conductor is at least partially aligned with thedie. The terminals on the chip carrier optionally may be movable withrespect to the die. The thermal conductor optionally may be movable withrespect to the die. An encapsulant layer may be provided between the dieand the chip carrier, and between the die and the thermal conductor.

The circuit panel has contact pads and has a thermal conductor mounting.The pads and thermal conductor mounting typically are metallic. Thepackaged chip is disposed on the circuit panel so that the outer surfaceof the chip carrier faces toward the circuit panel. The terminals of thechip carrier are bonded to the contact pads of the circuit panel. Mostdesirably, the thermal conductor of the chip carrier is also bonded tothe thermal conductor mounting of the circuit panel, and this bondpreferably is a metallurgical bond. As used in the disclosure, the term“metallurgical bond” refers to a connection between elements formedsubstantially or entirely from one or more metals or alloys. The thermalconductor and the bond between the thermal conductor and the thermalconductor mounting on the circuit panel provide a low thermal resistancecooling path between the packaged chip and the circuit panel. Moreover,the thermal conductor can attenuate undesired RF emissions from the chipand/or RF signals impinging on the chip from other portions of thecircuit, and can also be referred to as a “shield.” Most desirably, thethermal conductor mounting of the circuit panel is connected to a groundor power voltage source and the thermal conductor is electricallyconnected to one or more ground or power contacts on the die by thermalconductor leads similar to those used to connect the other contacts withthe terminals. Thus, the thermal conductor can act as a very largeground or power terminal. Because the thermal conductor has asubstantial horizontal extent, the thermal conductor can also act as aground or power distribution bus; in this case, the thermal conductor iselectrically connected to numerous ground contacts or numerous powercontacts at widely spaced locations on the die. In a variant of thisapproach, the thermal conductor may serve as a clock terminal and/orclock distribution bus, in which case the thermal conductor mount on thecircuit panel is connected to a clock signal bus so that the clocksignal is routed between the clock signal bus and the clock contacts ofthe chip.

In certain embodiments, the packaged chip may include a metallic heatspreader or “can” having a main or top wall structure overlying the rearsurface of the chip so that a portion of the heat spreader facesupwardly, away from the circuit panel when the packaged chip isassembled to the circuit panel. The heat spreader desirably has a sidewall projecting from the main portion of the heat spreader towards thefront surface of the die. This wall desirably terminates in a horizontalsurface or flange. In the assembly, the horizontal surface or flange ofthe heat spreader desirably is metallurgically bonded to a spreadermounting on the circuit panel. The spreader facilitates heat transferfrom the packaged chip into the surroundings, away from the circuitpanel. Where the spreader is bonded to the circuit panel, the spreadercan also facilitate transfer of heat from the packaged chip into thecircuit panel. The spreader can also serve as an RF shield, as a groundconnection to the rear surface of the chip, or both. In an alternativearrangement, the side wall structure is bonded to a metallic feature onthe chip carrier, which in turn is bonded to a mating feature of thecircuit panel.

Yet another aspect of the invention provides packaged chips havingfeatures as discussed above in connection with the assembly.

A still further aspect of the invention provides connection componentssuitable for use in fabricating the packaged chips. Connectioncomponents according to this aspect of the invention most preferablyinclude a dielectric layer having an inner surface and an outer surface,a metallic thermal conductor occupying at least a part of the dielectriclayer, and terminals on the dielectric layer. The thermal conductor hasan area substantially larger than the area of each individual terminal.The terminals and the thermal conductor are exposed at the outer surfaceof the dielectric layer. For example, the terminals and the thermalconductor may overlie the outer surface. Alternatively, the terminalsand the thermal conductor may be disposed on the inner surface andopenings in the dielectric layer may be provided in alignment with theterminals and the thermal conductor. The connection component desirablyincludes terminal leads electrically and physically connected to theterminals and most preferably includes one or more thermal conductorleads electrically and physically connected to the thermal conductor.The terminals, leads and thermal conductor are arranged so that when theleads are connected to the contacts on the die the thermal conductoroverlies the front surface of the die. For example, the thermalconductor may be disposed in a central region of the dielectric layer,and at least some of the terminals may be disposed in a peripheralregion of the dielectric layer surrounding the central region.

Most desirably, the terminals, lead and thermal conductor are all formedin a single metallization layer as, for example, by etching a singlelayer of metal. In one preferred arrangement, the leads extend acrossgaps in the dielectric layer so that the leads can be engaged withcontacts on the chip during formation of a chip package by advancing abonding tool into the gap so as to force the leads into engagement withthe contacts on the chip. Most desirably, each lead includes aconnection section which will be engaged with a contact on the chip anda frangible section weaker than the connection section. The frangiblesections of the terminal leads may be disposed between the connectionsections of these leads and the thermal conductor. Thus, prior toassembly with the chip, the terminals and terminal leads areelectrically connected in common by the thermal conductor. However, whenthe frangible sections of the terminal leads are broken, the terminalleads are electrically disconnected from the thermal conductor. Thisallows use of the thermal conductor as a commoning bus duringfabrication of the leads as, for example, in electroplating or etchingoperations.

A further aspect of the invention provides a packaged semiconductorchip. The packaged chip according to this aspect of the inventiondesirably includes a first semiconductor chip having an upwardly-facingfront face, a downwardly-facing rear face, edges bounding said faces andcontacts exposed at said front surface, said first semiconductor chipincluding active components. A connecting element including passivecomponents such as resistors, capacitors and inductors is electricallyconnected to at least some of the contacts of the first chip. Theconnecting element overlies the front face of the first chip andprojects outwardly beyond the edges of the first chip. A chip carrier isdisposed below the rear surface of the first chip. The chip carrier hasa bottom surface facing downwardly away from the first chip and has aplurality of terminals exposed at the bottom surface, at least some ofsuch terminals being electrically connected to at least some of thecontacts of the first chip through said connecting element. Mostpreferably, the connecting element is a second chip incorporating thepassive elements, also referred to as a “passive chip.” The chip carriermay include a thermal conductor as discussed above, and may also includea spreader or enclosure having a top wall overlying the rear surface ofthe connecting element or passive chip. As discussed above, thesefeatures provide further enhanced thermal dissipation andelectromagnetic shielding.

In a packaged chip according to a further aspect of the invention, theposition and orientation of the first chip and the connecting element orpassive chip are reversed, so that the first chip lies above the passivechip. In this arrangement, the front surface of the first or active chipfaces downwardly and confronts the upwardly-facing surface of the secondor passive chip. The rear surface of the passive chip faces downwardly,toward the chip carrier. Chip assemblies according to this aspect of thepresent invention may also include thermal conductors and spreaders asdiscussed above.

Yet another aspect of the present invention provides packaged modulesincluding two separate microelectronic circuits a pair of separate radiofrequency amplification circuits. A packaged module according to thisaspect of the invention includes a carrier having top and bottomsurfaces and having terminals exposed at the bottom surface. A firstmicroelectronic unit or assemblage including one or more chips ismounted to the carrier and overlies a first region of the top surface. Asecond microelectronic unit or assemblage is also mounted to the carrierand overlies a second region of the chip carrier. The module accordingto this aspect of the invention most preferably includes a metallicenclosure having top wall structure extending above the microelectronicunits or assemblages and side wall structure extending downwardly fromthe top wall structure to the vicinity of the carrier. The enclosurealso desirably has a medial wall extending to the vicinity of saidcarrier between the first and second regions. The enclosure, andparticularly the medial wall structure, electromagnetically shields thefirst and second microelectronic units or assemblages from one another.Moreover, the enclosure desirably is in thermal communication with thechip or chips included in the microelectronic units or assemblages. Thepreferred modules according to this aspect of the invention can be used,for example, to provide a surface-mountable RF amplification unit whichincorporates a pair of separate radio frequency amplification circuits.

A further aspect of the invention provides a packaged surface acousticwave or “SAW” device. The packaged device according to this aspect ofthe invention includes a SAW chip having an acoustically active regionon its front surface. The SAW chip desirably is mounted front-face-downon a chip carrier having an inner surface and an outer surface so thatthe active region of the SAW chip front surface is aligned with a holein the chip carrier. The front surface is sealingly connected to thechip carrier around the periphery of the hole, so that the active regionof the SAW chip is maintained free of encapsulants and contaminants.Preferred structures according to this aspect of the invention canprovide a thin, surface-mountable packaged SAW device at low cost.

Yet another aspect of the invention provides A packaged semiconductorchip assembly including a first semiconductor chip incorporating one ormore active components together with a passive chip incorporating one ormore passive components selected from the group consisting of resistorsand capacitors. The packaged chip according to this aspect of theinvention also includes a chip carrier having terminals thereon. Thechips are secured to the chip carrier, and at least some of theterminals are connected to at least one of said chips. The packaged chipaccording to this aspect of the invention desirably includes at leastone inductor defined at least in part by features on the chip carrier,the at least one inductor being connected to at least one of the chips.As further explained below, the use of a passive chip to provide atleast some of the resistors and capacitors affords significant savingsin space and cost as compared to the use of discrete passive components,whereas formation of the inductor at least in part on the chip carrierallows the use of thick, low-resistance windings in the inductor toprovide inductors with a high quality factor or “Q.”

Still further aspects of the invention provide particular structures forinductors usable in the foregoing aspects of the invention and in otherapplications.

Additional aspects of the invention provide methods of mounting chips tocircuit panels. Methods according to this aspect of the inventiondesirably use packaged chips or modules and circuit panels as discussedabove. In a method according to this aspect of the invention, theterminals are bonded to the contact pads and the thermal conductor isbonded to the thermal conductor mounting in a single operation. Mostpreferably, the terminals and thermal conductor are soldered orotherwise metallurgically bonded to the contact pads and to the thermalconductor mounting. Preferably, the contact pads and the thermalconductor carry layers of solder before the packaged chip is assembledto the circuit panel. Alternatively, the solder may be provided on thecontact pads and on the thermal conductor mounting of the circuit panel.In either case, the solder connections can be relatively thin layers ofsolder as, for example, 25-50 microns thick. Stated another way, theconnection between the packaged chip and the circuit panel may be a“land grid array” rather than a ball grid array. The ability to use thinsolder connections further enhances the electrical performance of thecompleted assembly, and minimizes the height of the assembly. Moreover,there is typically no need for a layer of dielectric material or“underfill” surrounding the solder connections between the connectioncomponent and the circuit panel. This simplifies the connectionprocedure. Where a heat spreader is to be bonded to a spreader mountingon the circuit board, the spreader desirably is provided in place on thechip package before the chip package is assembled to the circuit panel,and the spreader is bonded to the circuit panel in the same bondingoperation used to bond the terminals and thermal conductor.

The features of the foregoing aspects of the invention can be combinedwith one another or used separately. Still other objects, features andadvantages of the present invention will be more readily apparent fromthe detailed description of the preferred embodiments set forth below,taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sectional view of an assembly in accordancewith one embodiment of the invention, including a packaged chip and acircuit board.

FIG. 2 is a diagrammatic plan view of the packaged chip depicted in FIG.1 during one stage of manufacture.

FIGS. 3, 4 and 5 are diagrammatic sectional views of packaged chips inaccordance with further embodiments of the invention.

FIG. 6 is a diagrammatic perspective view of a component in accordancewith a further embodiment of the invention.

FIG. 7 is a diagrammatic sectional view of an assembly in accordancewith a further embodiment of the invention.

FIG. 8 is a diagrammatic sectional view of a module in accordance withyet another embodiment of the invention.

FIG. 9 is a fragmentary, diagrammatic perspective view of a component inaccordance with a further embodiment of the invention prior toconnection to a chip.

FIG. 10 is a fragmentary, diagrammatic sectional view of a packaged chipincorporating the component of FIG. 9.

FIG. 11 is a fragmentary, diagrammatic sectional view of a packaged chipaccording to a further embodiment of the invention.

FIG. 12 is a fragmentary, diagrammatic plan view of a componentincorporated in the packaged chip of FIG. 11.

FIG. 13 is a fragmentary, diagrammatic perspective view of a componentin accordance with yet another embodiment of the invention.

FIG. 14 is a diagrammatic sectional view taken along line 14-14 in FIG.13.

FIG. 15 is a fragmentary, diagrammatic plan view of a component inaccordance with yet another embodiment of the invention.

FIG. 16 is a fragmentary perspective view of a component according toyet another embodiment of the invention.

FIG. 17 is a fragmentary sectional view taken along line 17-17 in FIG.16.

FIG. 18 is a fragmentary plan view of a packaged chip according to yetanother embodiment of the invention.

FIG. 19 is a fragmentary perspective view showing a portion of the chipincorporated in FIG. 18.

FIG. 20 is fragmentary, diagrammatic perspective view depicting certainelements in the packaged chip of FIGS. 18 and 19.

FIG. 21 is a diagrammatic sectional view of a module in accordance withyet another embodiment of the invention.

FIG. 22 is a fragmentary sectional view on an enlarged scale of aportion of the module shown in FIG. 21.

FIGS. 23 and 24 are diagrammatic sectional views of packaged chipsaccording to still further embodiments of the invention.

FIG. 25 is a fragmentary top plan view of a component used in a methodaccording to a further embodiment of the invention.

FIG. 26 is a fragmentary bottom plan view of a further component used inconjunction with the component of FIG. 25.

FIG. 27 is a fragmentary, diagrammatic sectional view depicting anassembly made using the components of FIGS. 25 and 26 at a stage ofmanufacture.

FIG. 28 is a diagrammatic elevational view of a unit formed from theassembly of FIG. 27.

FIG. 29 is a diagrammatic sectional view of an assembly in accordancewith yet another embodiment of the invention.

FIG. 30 is a diagrammatic top plan view of a component in accordancewith a still further embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 shows a diagrammatic sectional view of a chip assembly accordingto one embodiment of the invention. The assembly includes a packagedchip 10 mounted to a circuit board 12. The packaged chip 10 includes achip or “die” 14 and a chip carrier 16. FIG. 2 shows a diagrammatic planview of the die 14 and chip carrier 16 of FIG. 1 at an intermediatestage during fabrication of the packaged chip. The chip carrier 16includes a dielectric layer 18 which desirably is a thin, flexible layerof a polymeric dielectric as, for example, polyimide or BT resin. Thechip carrier has a large metallic thermal conductor 20 in a centralregion and a plurality of terminals 22 in a peripheral regionsurrounding the central region. The dielectric also has apertures orbond windows 24 extending through the dielectric between the terminalsand the thermal conductor. Each terminal 22 has a terminal lead 26associated with it. Each terminal lead 26 has a connection sectionprojecting inwardly from the associated terminal across one of the bondwindows 24. Each terminal lead also has a frangible section 28 betweenthe connection section and the thermal conductor, so that the connectionsections of the various terminal leads are connected to the thermalconductor through the frangible sections.

A few of the leads are thermal conductor leads 30. The thermal conductorleads are similar to the terminal leads except that the connectionsections of the thermal conductor leads are connected directly tothermal conductor 20, without an intervening frangible section. The endof the connection section of each thermal conductor lead 30 remote fromthermal conductor 20 is connected to a “dummy” terminal 22 a by afrangible section 32. Thus, the frangible sections of the thermalconductor leads are disposed adjacent the outer edges of the bondwindows 24, remote from thermal conductor 20.

The terminals, leads and thermal conductor form an electricallycontinuous structure. Thus, the leads can be plated or otherwisesubjected to processes requiring electrical current without the need forany additional electrical commoning element. Preferably, the thermalconductor, leads and terminals are formed from a single layer of copperor copper alloy about 10-30 microns thick, more preferably about 15-20microns thick, on the dielectric layer. A photoresist can be applied andpatterned using conventional techniques so that regions of the copper orcopper alloy layer can be selectively removed so as to leave theterminals, thermal conductor and leads in place. In other processes, thethermal conductor, leads and terminals can be formed by selectivedeposition of one or more metals, such as by patterning a photoresistand plating in areas which are not covered by the photoresist. The bondwindows can be formed by etching the dielectric or by exposing thedielectric to radiation such as laser radiation. The fabricationprocedure for the chip carrier can be essentially as shown and describedin the patents incorporated by reference. Also, although the frangiblesections 28 and 32 are illustrated in FIG. 2 as having width less thanthe width of the connection sections, essentially any type of frangiblesection can be employed. For example, the leads may incorporatefrangible sections of reduced thickness and/or of differentmetallurgical structure and/or composition from the connection sections.

In fabrication of the package semiconductor chip, a die 14 is juxtaposedwith the chip carrier so that the front surface 35 of the die facestoward the chip carrier and so that contacts 34 on the die aresubstantially aligned with the bond windows and with the connectionsections of the terminal leads. Desirably, the arrangement of the leadsis selected so that ground contacts on the die are aligned with thethermal conductor leads. In one manufacturing process, the dielectric issupported temporarily above the front or contact bearing surface of thedie by a porous layer formed from a plurality of compliant elements or“nubbins” 36 (FIG. 1). As described in U.S. Pat. Nos. 5,706,174;5,659,952; and 6,169,328, the disclosures of which are incorporated byreference herein, the nubbins typically are provided on the innersurface of the dielectric which faces toward the die. The connectionsections of leads 26 and 30 may be bonded to the contacts by advancing atool such as an ultrasonic or thermosonic bonding tool into the bondwindows 24 so as to displace each connection section toward the die.This action breaks the frangible sections of the leads. Thus, theterminal leads 26 remain connected to terminals 22, and these terminalsare disconnected from the thermal conductor. The thermal conductor leads30 are disconnected from the associated dummy terminals 22 a but remainconnected to thermal conductor 20. Thus, at the end of the bondingprocess, the signal contacts 34 on the die are connected to theterminals whereas the ground contacts 34 a are connected to the thermalconductor. The thermal conductor also serves as an anchor or support tofacilitate breakage of the frangible sections associated with theterminal leads.

Following connection of the leads, the assembly is encapsulated byinjecting a flowable, typically liquid encapsulant 40 between the dieand the dielectric layer of the connection component. The encapsulantdesirably also covers the edges 46 of the die, but does not cover therear surface of the die. Techniques for applying an encapsulant aredisclosed, for example, in U.S. Pat. Nos. 5,766,987; 6,049,972; and6,046,076, the disclosures of which are also incorporated by referenceherein. Typically, several connection components are provided assections of a single dielectric layer tape, which incorporates severalsets of terminals and several thermal conductors as aforesaid. Severalchips are assembled to the various sets of terminals, and encapsulated,whereupon the tape is severed to provide individual packaged chips.

Other manufacturing processes can be employed. For example, the die canbe attached to the connection component by a preformed pad of anadhesive material or “die attach” disposed between the front face 35 ofthe die and the connection component. Such a pad can be provided as apart of the connection component, or applied during the assemblyoperation. In another technique, die attach material is provided betweenthe front face of the die and the connection component by dispensing amass of uncured, flowable die attach onto the connection component oronto the die before assembling the die to the connection component.

After encapsulation, the packaged semiconductor chip has theconfiguration shown in FIG. 1. As best seen in that figure, theconnection sections of the leads 26, 30 are bent toward the die and incontact with the contacts 34, 34 a of the die. The encapsulant layerextends between the die and the dielectric element. In this embodiment,the terminals and thermal conductor are disposed on the bottom or outersurface 42 of the dielectric (the surface facing downwardly, away fromthe die in FIG. 1) and hence are exposed at this surface. Theencapsulant surrounds the die but desirably does not overlie the rearsurface 44 of the die, remote from the dielectric layer.

In this embodiment, the terminals are disposed outside of the lateraledges 46 of the die. Stated another way, the terminals “fan out” fromthe die. Because the encapsulant is not directly loaded in shear betweena terminal overlying the surface of the die and the die itself,substantial movability of the terminals can be achieved even with anencapsulant having a substantial shear modulus and a substantial modulusof elasticity. Typical encapsulants such as silicone gels tend to havecoefficients of thermal expansion (“CTE”) substantially greater thanthat of the die and substantially greater than that of a circuit boardto which the packaged chip will be mounted. In a fan-out structure, thefatigue stresses imposed on the leads during thermal cycling arise tosome extent from the expansion of the encapsulant itself. Therefore, itis desirable to minimize the CTE of the encapsulant. For commonencapsulants, there is an inverse relationship between CTE and modulusof elasticity. Thus, an encapsulant having lower CTE normally will havehigher modulus of elasticity and higher shear modulus. Accordingly, theencapsulant 40 used in this embodiment desirably has a coefficient ofthermal expansion less than about 200×10⁶/° C. and more desirably lessthan about 100×10⁶/° C. The encapsulant in this embodiment preferablyhas a modulus of elasticity between 0.1 GPa and 3 GPa, typically between0.5 GPa and 3 GPa, as measured at room temperature. It is desirable tominimize variation in the properties of the encapsulant with temperatureas, for example, in the range of temperatures from −65° C. to +125° C.As the thermal conductor 20 overlies the front or contact-bearingsurface 35 of the die, that portion of the encapsulant disposed betweenthe thermal conductor and the die will be in direct shear between thedie and the thermal conductor due to differential thermal expansion andcontraction of these elements. However, strain in this portion of theencapsulant is limited because the entire thermal conductor lies closeto the center of the die. Moreover, the bond between the thermalconductor 20 and the thermal conductor mounting of the circuit panel 12,discussed further below, covers a substantial area and thus hassubstantial strength and fatigue resistance. For this reason as well,stress on this bond due to thermal effects tends to be less criticalthan stress on the bonds between the terminals and the contact pads. Ina variant of this embodiment, the encapsulant may have non-uniformcomposition and properties as discussed below with reference to FIG. 3.

The packaged semiconductor chip is provided with thin layers of solder50 on the terminals 22, 22 a and with a thin layer of solder 52 onthermal conductor 20. Such thin layers can be applied by application ofsolder paste and subsequent volatilization of the organic carrier fromthe paste or by wave-soldering or dip-soldering techniques. Desirably,the solder layers are less than about 75 microns thick, most preferablybetween 25 and 50 microns thick. The solder layers can be applied beforesevering the tape to form individual packaged chips.

In an assembly technique according to a further aspect of the invention,the packaged semiconductor chip is assembled to a circuit board or othercircuit panel 12 as shown in FIG. 1. In a single operation, usingconventional surface-mounting soldering techniques, the terminals aresoldered to the contact pads 54 of the circuit board, whereas thethermal conductor 20 is soldered to the thermal conductor mounting 56 ofthe circuit board. Most preferably, the bond between the thermalconductor and the thermal conductor mounting covers substantially theentire surface area of the thermal conductor, as, for example, at leastabout 80% of the thermal conductor surface area. Only a small fractionof the circuit board is illustrated. The contact pads 54 of the circuitboard are connected by surface or internal connections of circuit panel12 to appropriate signal-carrying traces and other electrical featuresof the circuit board, whereas the thermal conductor mounting 56desirably is connected to a source of ground potential or other constantpotential. Thus, after soldering the die is electrically connected tothe appropriate signal connections of the circuit board through theterminals 22 and signal leads 26, whereas the die is connected to groundthrough the thermal conductor leads 30, thermal conductor 20 and thermalconductor mounting 56. The entire structure is quite thin. Typically,the entire structure is less than about 0.8 mm thick and more preferablyless than 0.6 mm thick. In one example, the dielectric layer of the chipcarrier is about 25-75 μm thick, and most desirably about 50 μm thick.The terminals, leads and thermal conductor are about 10-25 μm thick, anddesirably about 18 μm thick, whereas the solder lands used to connectthe structure to the circuit board are about 25-50 μm thick. In thisembodiment, the encapsulant layer between the front face of the chip andthe inner surface of the chip carrier is about 50-75 μm thick. The frontface of the chip lies about 180 μm above the face of the circuit boardwhen the assembly is mounted on the circuit board. These thicknesses aremerely illustrative.

The thermal conductor 20 and the metallic bond between the thermalconductor and the thermal conductor mounting of the circuit boardprovide a thermally conductive heat transfer path from the die into thecircuit board and also provide electrical shielding between the die andthe circuit board. The entire structure is rugged and reliable. Interalia, the bond between the thermal conductor and the thermal conductormounting mechanically secures the packaged chip in place.

The packaged chip illustrated in diagrammatic sectional view in FIG. 3is similar to the packaged chip discussed above. However, the thermalconductor 120 and terminals 122 are disposed on the inner surface of thedielectric. Openings 124 are formed in the dielectric in alignment withthe terminals and another opening 126 is formed in alignment withthermal conductor 120 so that the terminals 122 and thermal conductor120 are exposed at the outer surface 142 of the dielectric. Mostpreferably, the openings in the dielectric at the terminals and thethermal conductor are not plated. Rather, the bonding material such assolder 150 which is used to secure the packaged chip to the circuitboard extends through the openings. This avoids the need for expensiveplating operations. If desired, a ring of solder-wettable metal may beprovided on the outer surface 142 around each such opening to controlthe shape of the solder masses.

Also, in the embodiment of FIG. 3, the terminals 122 are disposed in aregion of the connection component which is disposed in alignment withthe front surface 135 of the chip. The terminal leads “fan-in” orproject inwardly towards the geometric center of the chip from thecontacts on the chip to the terminals. Thus, the terminals are disposedinside the area bounded by the bond windows 124. An anchor 160 isdisposed on the opposite side of the bond windows from the terminals.Prior to assembly with the die, the connection sections of the terminalleads 126 are connected to anchors 160 by frangible elements disposedadjacent the anchors. In this embodiment, the thermal conductor leads130 are also connected to the anchors by frangible elements disposedadjacent to the anchors. The thermal conductor leads extend in regionswhich are not occupied by terminals and terminal leads. In thisarrangement, the anchors serve as electrical commoning for platingduring fabrication of the connection component. In the embodiment ofFIG. 3, the encapsulant is of non-uniform composition. The region of theencapsulation disposed between the die and the thermal conductor hashigh thermal conductivity. Such high thermal conductivity can beimparted, for example, by adding thermally conductive filler to theencapsulant. Preferably, the filler itself is dielectric as, forexample, boron nitride or alumina. Electrically conductive fillers suchas silicon nitride or metals can be employed, preferably inconcentrations and in particle sizes such that the encapsulant as awhole, even with the conductive filler, is electrically insulating. Theportion 141 of the encapsulant surrounding the connection sections ofthe leads need not incorporate such a thermally conductive filler. Also,in this embodiment, the encapsulant 141 surrounding the connectionsections of the lead and the periphery of the die may have physicalproperties different from that of the encapsulant 143 disposed betweenthe die and the thermal conductor. For example, the modulus ofelasticity of the encapsulant surrounding the leads may be 100 Mpa orless. In a further variant, the border between the two different typesof encapsulants can be displaced inwardly, toward the thermal conductorand toward the center of the die front face, from the position depictedin FIG. 3, so that the softer, lower-modulus encapsulant 141 is disposedbetween the die and the terminals. The stiffer, higher-modulus and morethermally conductive encapsulant 143 is disposed between the die and thethermal conductor.

In the embodiment of FIG. 3, as in the embodiment of FIG. 1, the thermalconductor, the terminals and the leads are all formed from a singlelayer of a conductive metal such as copper or copper alloy. Placement ofthis layer on the side of the dielectric facing toward the die, referredto as a “circuits in” configuration, as in FIG. 3, provides the minimumpackage thickness and provides the maximum solder pad thickness for agiven package thickness. However, an arrangement with the thermalconductor and terminals on the side of the dielectric facing away fromthe die, commonly referred to as a “circuits out” configuration, as inFIG. 1, provides additional spacing between the die and the thermalconductor. This can be advantageous where the die has components such asinductors which interact with a thermal conductor disposed in closeproximity to the die.

The packaged chip shown in FIG. 4 has the “fan-out” arrangement of thepackaged chip shown in FIGS. 1 and 2, but has the thermal conductor 220and terminals 222 disposed on the inner or upper surface 238 of thedielectric layer as discussed above with reference to FIG. 3. Also, thepackaged chip incorporates an element referred to herein as a heatspreader or enclosure 270 having a main portion or top wall structure271 overlying the rear face 244 of the die (the face facing upwardly inFIG. 4) and having a side wall structure 272 projecting downwardly,beyond the front face 235 of the die to the vicinity of the chip carrier212, at the periphery of the packaged chip. The side wall structure 272desirably extends around the entire periphery of the packaged chip, butcan be interrupted at locations located along the periphery of the chip.The side wall structure 272 terminates, at its bottom edge, in a flange274 having a horizontal face 276 facing downwardly and hence facing inthe same direction as the outer surface of the chip carrier. Desirably,the bottom edge of the side wall structure is disposed near the bottomsurface 142 of chip carrier 212. The spreader or enclosure 220 can beformed from a metal such as copper, a copper alloy, aluminum or otherthermally conductive metal. The spreader or enclosure 220 may have someflexibility so that the flange 274 can be displaced in the upward anddownward direction during mounting as disclosed in U.S. Pat. No.6,075,289, the disclosure of which is incorporated by reference herein.Desirably, at least the horizontal surface of the flange 276 is formedfrom or covered by a metal suitable for soldering. During manufacture,encapsulant 241 is injected or otherwise introduced into the interior ofthe hollow can or spreader 270. Flange 276 may be maintained free ofencapsulant by providing a solder mask layer or other temporary layer(not shown) covering the flange and bridging the gap between the flangeand the chip carrier. This temporary layer is removed after theencapsulant is cured. When the packaged chip is assembled to the circuitboard 280, the horizontal surface 276 of the flange is soldered to ametallic spreader-mounting element 281 on the circuit board. Thespreader-mounting element on the circuit board desirably is connected toa ground bus in the circuit board. The spreader or enclosure 270provides additional heat dissipation capacity and also providesadditional electrical shielding. As in the embodiment discussed abovewith reference to FIG. 3, the encapsulant desirably includes regionshaving different physical properties. Here again, the encapsulant 243 inthe region disposed between the die and the thermal conductor desirablyhas high thermal conductivity. The space between the rear surface of thedie and the main portion or top wall structure 271 of the spreader orenclosure 270 is filled with an encapsulant 245 having high thermalconductivity. This encapsulant also may be electrically conductive so asto form a ground connection to the rear surface of the die. Encapsulant245 may be a composition including a polymer and a metal, or may be ametallic material such as a solder. In some cases, the entire rearsurface of the die serves as a ground plane. Other dies have groundcontacts 202 at specific locations on the rear surface. These contactsmay be recessed into the rear surface, in depressions 204 open to therear surface so that the contacts are exposed at the rear surface. Forexample, dies formed from gallium arsenide often are provided with suchrear-surface ground contacts. Where the encapsulant 245 overlying therear surface is electrically conductive, it desirably abuts the rearsurface ground contacts 202 and desirably extends into depressions 204.This provides additional thermal conductivity from within the die tospreader or enclosure 270. In yet another variant, the encapsulant mayextend into depressions 204 to provide enhanced thermal conductivityeven if contacts 202 are not used. The encapsulant 241 surrounding leads226 may have a lower modulus of elasticity than the encapsulant 245 atthe rear surface.

In the embodiment of FIG. 5, the terminal leads 326 are connected to thecontacts 334 on the die and formed into a vertically extensivedisposition by a process similar to that described in U.S. Pat. Nos.5,518,964; 5,830,782; 5,913,109; and 5,798,286 the disclosures of whichare also incorporated by reference herein. As discussed in certainpreferred embodiments of the '964 patent, leads which are initiallyprovided on the connection component or chip carrier may have anchorends connected to the terminals and tip ends remote from the terminals.The tip ends may be releasably secured to the connection component. Allof the tip ends can be bonded to the various signal contacts on the chipin a single operation. After bonding the chip ends to the contacts, thedie and the connection component are moved away from one another for acontrolled, predetermined displacement thereby moving the tip ends ofthe leads away from the connection component and deforming the leads toa vertically extensive disposition. Alternatively, the signal leads 326can be provided on the die. In this case, the tip ends are bonded to theterminals or to other structures of the connection componentelectrically connected to the terminals before the die and theconnection components are moved away from another. The thermal conductorleads 330 which connect the thermal conductor 320 to the ground contactson the die are formed in the same manner. Desirably, both the terminalleads and the thermal conductor leads are deformed to a verticallyextensive disposition in the same movement of the die and connectioncomponent. The encapsulant 340 may be injected during or after themovement process. Because all of the leads in a given package can beconnected and formed in a single operation or the package canincorporate numerous leads without substantial added cost. Inparticular, numerous thermal conductor leads 330 may be provided. Thenumber of thermal conductor leads may exceed the number used for makingthe ground connections to ground contacts on the chip. The extra leadsmay be connected to “dummy” or unused contacts on the front surface ofthe chip. These dummy contacts need not be connected to internalelectrical components of the chip. The numerous thermal conductor leadsserve as metallic heat conductors extending between the die and thethermal conductor and further enhance the thermal properties of thepackage. In a variant of this approach, the thermal conductor leadswhich serve as active ground conductors, the thermal conductor leadsconnected to dummy contacts, or both may incorporate structures asdisclosed in U.S. Pat. No. 5,557,501, the disclosure of which is alsoincorporated by reference herein. Also, as disclosed in U.S. Pat. No.5,976,913, also incorporated by reference herein, movement of the dieand the connection component in a deformation process can be controlledby restraining straps which are shorter and stronger than the otherleads used in the assembly. Some or all of the thermal conductor leadscan be formed as restraining straps.

Other forms of leads can be employed. For example, as disclosed in U.S.Pat. No. 6,228,686, the disclosure of which is hereby incorporated byreference herein, a sheet-like element may include a main region andlead region which are partially segregated from the main region by slotsextending around each lead region. The slot extending around eachparticular lead region is interrupted at a fixed end of the lead so thatthe fixed end remains attached to the main region of the sheet. Theconnection component diagrammatically depicted in FIG. 6 has terminalleads 426 and thermal conductor leads 430 made in this manner. Thus,each of the tip ends 403 of terminal leads 426 is surrounded by aU-shaped slot 405 which extends toward the terminal 422 attached to suchlead. Each terminal lead includes a conductive strip 425 attached to aportion of the dielectric layer 418 disposed inside slot 405. Theterminals 422 are disposed on the inner or upper surface of thedielectric layer openings 407 provided to expose the terminals at thelower or outer surface of the dielectric. In this embodiment, thethermal conductor 420 is also disposed on the inner surface of thedielectric layer. Thermal conductor 420 extends beyond the opening 401in the dielectric layer 418 which is used to expose the thermalconductor at the outer surface. Thus, the thermal conductor partiallysurrounds those regions of the sheet which constitute the terminal leadsso as to provide additional RF shielding in the completed assembly.Thermal conductor lead 430 is formed by a portion of thermal conductor420 surrounded by a U-shaped slot 431. In use, the tip ends of theterminal leads and the tip end of the thermal conductor lead are bondedto contacts on the die and the die and connection component are movedaway from one another so as to bend the various leads out of the planeof the sheet in the manner described in the '501 patent. The reversearrangement, with the conductive strips and thermal conductor on thelower or outer surface of the dielectric, also can be used. In thisreverse arrangement, holes are formed in the dielectric at the tip endsof the terminal leads.

In the embodiments discussed above with reference to FIGS. 1-6, thethermal conductor is provided in a central region of the connectioncomponent, aligned with the central region of the die front face.However, this is not essential. Thus, as depicted in FIG. 7, a die 514may have contacts 534 disposed adjacent the center of the die front face535. In this case, the thermal conductor 520 may be disposed adjacentthe periphery of the die whereas the terminals may be disposed adjacentthe center of the die.

Numerous further variations and combinations of the features discussedabove can be utilized without departing from the present invention. Forexample, leads of the types shown in FIGS. 1-6 can be used in anassembly configured as shown in FIG. 7. Also, bonding materials otherthan solder may be employed to form the metallurgical bonds of thevarious assemblies. For example, the terminals, thermal conductor and/orspreader can be bonded to the metal elements of the circuit board byprocesses such as eutectic bonding, diffusion bonding, welding orthermosonic bonding, or by use of a composite material such as ametal-filled polymer, as, for example, a silver-filled epoxy. In theembodiments discussed above, the terminal leads which carry the signalsare in the form of elongated strips having generally rectangularcross-sectional shapes when seen in sectional view along a cutting planeperpendicular to length of the lead. Short, strip-like leads are highlypreferred because they provide low inductance connections between theterminals and the contacts of the chip. Desirably, each terminal leadhas inductance below 0.3 nH and desirably below 0.2 nH. For even greatercontrol of lead impedance, the leads can be provided as multi-conductorleads of the types described in published International PatentApplication PCT/US96/14965, the disclosure of which is also incorporatedby reference herein. As described therein, such a multi-conductor leadcan incorporate a ground conductor or other constant-potential conductorextending parallel to the actual signal conductor, so as to form astripline having well-controlled impedance. Alternatively oradditionally, a multi-conductor lead can be used as a differential linein which one conductor carries a first copy of the signal and anotherconductor carries a further copy of the signal having the opposite sign.Such a differential signaling scheme provides substantial immunity tonoise and also suppresses radiation of the signal from the line.

A packaged semiconductor module according to a further embodiment of theinvention (FIG. 8) includes a first semiconductor chip 614 incorporatingactive semiconductor components. As used in this disclosure, the term“active semiconductor component” should be understood as referring tocomponents such as transistors having a switching, amplification,photoelectric, light-emitting or other function different fromresistance, capacitance and inductance. Most common semiconductor chipssuch as processors and memory chips incorporate thousand or millions ofactive components. Moreover, analog or mixed digital/analog chips suchas radio frequency amplifiers also incorporate active components.Section 602 also includes a second chip 615 which incorporates at leastsome passive components and which preferably incorporates only passivecomponents. As used in this disclosure, the term “passive component”should be understood as referring to resistors, inductors andcapacitors. Also, the second chip 615 may or may not includesemiconductor material. As used in this disclosure, the term “chip”should be understood as referring to an element which includes activecomponents or which includes thin-film components, i.e., componentshaving thicknesses less than about 4 μm, or both. Thus, the term “chip”as used in this disclosure includes common semiconductor chips and alsoincludes components which consist of one or more thin-film componentsformed on dielectric materials such as glass or on semiconductorsmaterials such as silicon. Chips 614 and 615 are arranged to cooperatewith one another and cooperatively form a first microelectronicassemblage 602. The module also includes a second microelectronicassemblage 604 incorporating an active semiconductor chip 606 and apassive semiconductor chip 608. A chip carrier 616 is also provided. Thechip carrier is generally similar to the carriers discussed above. Hereagain, it includes a dielectric layer 618 and has a top or upper surface638 and a lower or bottom surface 642. The chip carrier has a first setof terminals 622 disposed in a first region 631 of the carrier and asecond set of terminals 623 disposed in a second region 633. The chipcarrier also has a first thermal conductor 620 in the first region 631of the carrier and a second thermal conductor 621 in the second region633. These elements of the chip carrier may be similar to thecorresponding elements of the chip carriers discussed above. The chipcarrier is provided with a first set of interconnecting conductiveelements 660 in the first region. Each such interconnecting elements 660includes a first lead 660 a, a trace 660 b and a second lead 660 c atthe opposite end of the trace. The second region is provided with asimilar set of interconnecting elements 661. Additionally, the chipcarrier has a central ground strip 662 which extends into and out of theplane of the drawing in FIG. 8. Ground strip 662 defines the borderbetween the first region 631 (to the left in FIG. 8) and the secondregion 633 (to the right in FIG. 8).

The first electronic assemblage 602 overlies the top surface 638 of thechip carrier in the first region. The first or active chip 614 isconnected by terminal lead 626 to the terminals 622 of the first set,and is also in thermal communication with the first thermal conductor620. The relationship between the first chip 614 and the first terminals622 and first thermal conductor 620 may be similar to those discussedabove. For example, an encapsulant 641 having a relatively high thermalconductivity may be used to provide intimate thermal communicationbetween the front or contact-bearing surface of first chip 614 (thesurface facing downwardly in FIG. 8) and the first thermal conductor620. The second or passive chip 615 of first assemblage 602 is connectedby the first conductive elements 660 to the first chip 614. Thus, leads660 a are bonded to contact (not shown) on first chip 614, whereas leads660 c of the same conductive elements are bonded to contacts on thesecond or passive chip 615. Also, the second or passive chip 615 ofassemblage 602 is connected by leads 664 to the central ground region662.

Chips 606 and 608, constituting second assemblage 604 are mounted inessentially the same way and overlie the second region 633 of the chipcarrier.

The module according to FIG. 8 also includes an enclosure 670. Theenclosure 670 may be generally similar to the enclosure discussed abovewith reference to FIG. 4. Thus, the enclosure includes a top wallstructure 671 extending above the chips of both assemblies and side wallstructure 672 extending downwardly from the top wall structure to thevicinity of chip carrier 618. Here again, the rear surfaces of thevarious dies desirably are in thermal communication with the top wallstructure 671. For example, a layer of an encapsulant die attach orsolder having relatively high thermal conductivity may be providedbetween the rear surfaces of chips 606, 608, 614 and 615 and the topwall structure 671. In this embodiment as well, the bottom edge of theside wall structure is adapted for connection to a circuit panel. Thus,the bottom edge is provided with a flange 674 arranged for solderbonding or other metallurgical bonding to a corresponding structure on acircuit panel. In this embodiment, however, the enclosure also includesa medial wall structure 675 extending downwardly from the top wallstructure 671. The medial wall structure 675 terminates in a plate 677.Plate 677 is metallurgically bonded to the central ground strip 662 and,thus, is both electrically and mechanically connected to the centralground strip 662. The central ground strip 662 desirably is bonded tothe mating element of the circuit panel when the module is mounted tothe circuit panel, as by one or more solder masses 667.

The enclosure 671 provides mechanical protection and reinforcement tothe packaged module. Moreover, the enclosure cooperates with thermalconductors 620, 621 and other metallic components of the chip carrier toprovide electromagnetic shielding for the components in both assemblages602 and 604. Additionally, the medial wall structure 675, in cooperationwith central ground strip 662, provides effective electromagneticshielding between the two assemblages. Thus, assemblage 602 iseffectively isolated from assemblage 604. This arrangement can be usedto provide such isolation for any type of electronic circuits. It isespecially useful in the case where multiple electronic assemblages mustbe provided in a compact unit. Merely by way of example, modulesaccording to this aspect of the invention can be used in elements of RFtransmitting and receiving circuits of cellular telephones. In such adual-band radio frequency power amplifier, one assemblage 602 provides aradio frequency power amplifier operating in a first frequency band,whereas another assemblage 604 provides a radio frequency poweramplifier operating in another frequency band. Both assemblages canoperate independently, without cross-talk or interference, even thoughthe components of both assemblages tend to emit substantial amounts ofelectromagnetic interference. In a variant of the structure shown inFIG. 8, each assemblage may be a unit which includes only one chip;similar advantages of electromagnetic isolation between units will beprovided.

However, in the case where each unit includes passive components inaddition to the active chip, fabrication of at least some of the passivecomponents in each assemblage in an integrated chip, such as passivechips 615 and 608, makes the module considerably more compact than itwould be if the passive components were provided as separate, discreteelements. Resistors and capacitors, in particular, can be fabricatedreadily in a chip. The materials and processing techniques to make thepassive chips 608 and 615 may be different from those used to make theactive chips 606 and 614. For example, the passive chips may be formedon materials such as glass rather than on silicon. In another example,the active chips may be formed in whole or in part from compoundsemiconductors such as III-V semiconductors or II-VI semiconductors,whereas the passive chips may be silicon-based chips. Thus, RF poweramplifier chips formed from gallium arsenide and related semiconductorscan be used in conjunction with silicon-based passive chips. In anotherexample, the second or passive chips can be made with a larger minimumfeature size or “line width” than the active chips, or vice-versa.Additionally, active chips originally made for use with discreteexternal passive components can be used in conjunction with the passivechips. Thus, compactness similar to that achievable by incorporating thepassive components in the active chip itself can be achieved without theexpense and difficulty of modifying the active chip itself.

Most preferably, at least some of the inductors used in the circuit areformed at least in part by the chip carrier or by the chip carrier inconjunction with leads and other structures extending to one or both ofthe chips. Although inductors can be fabricated in a passive or activechip, it is difficult to make inductors with high inductance and,particularly, with a high quality of factor or Q. The chip carriertypically is a “thick-film” structure, having metal layers more thanabout 2 μm thick, typically more than about 4 μm thick, and mostpreferably more than about 10 μm thick. Such thick layers commonly areformed by processes such as lamination of metal layers to a dielectric,plating or screen printing. Inductors formed at least in part in thechip carrier can employ large, thick, low-resistance conductors and canprovide high inductance values with resistance far lower than thatachievable in a thin film structure. Thus, it is desirable to provide atleast some of the inductors incorporated in the circuit as structuresdefined in part or in whole by elements of the chip carrier, by leadsextending between the chip carrier and a chip or both.

As depicted in FIGS. 9 and 10, a substrate such as a chip carrier orother connection component used in conjunction with a semiconductor chipmay include a dielectric layer 700 having a trace 702 extendinggenerally in a spiral pattern on the dielectric layer. Trace 702 hasleads 704 and 706 formed integrally with the trace. Thus, the trace andleads may be formed on a surface of the dielectric layer by a depositionprocess or by selective etching of a metallic layer overlying thedielectric layer. The connection component, and hence dielectric layer700, is provided with openings or bond windows 708 and 710 aligned withleads 704 and 706. As fabricated, the leads 704 and 706 may be providedwith anchors 712 and 716. As discussed above in connection with theterminal leads and thermal conductor leads, leads 704 and 706 may beconnected to their respective anchors by frangible sections 718 and 720,respectively, when the connection component is manufactured. When theconnection component or chip carrier is assembled with a chip 722, thespiral trace 702 overlies the front surface of the chip. Leads 704 and706 are connected to contacts 724 on the chip and disconnected fromtheir respective anchors, as seen in FIG. 10. The process used forconnecting these leads may be identical to the process used forconnecting the other leads such as the thermal conductor leads andground leads discussed above. This is particularly desirable, inasmuchas it avoids the need for separate processing steps and separateequipment.

As schematically illustrated in FIG. 11, a similar inductor can be madewith two spiral coils 703 and 705 overlapping one another on oppositesides of the dielectric layer. Here again, these coils may be connectedto a chip by leads 707 and 709, formed integrally with the coilsthemselves. Such an arrangement can be used to provide a high-valueinductor or a transformer. As best seen in FIG. 12, the lead 711 at theinside of spiral coil 703 (on the outer surface of the dielectric layer)may be disposed inside of one or more turns of the spiral coil 705 onthe inner surface of the dielectric layer. In this case, the inside lead711 may extend to the chip through a bond window in the dielectric layerinside of or between turns of the other coil 705.

As shown in FIG. 13, an inductor can be formed on a connection componentor chip carrier 750 having a planar or sheet-like structure includingone or more dielectric layers by a zigzag arrangement of conductors 752on a first side and conductors 754 on the opposite side of thestructure. These conductors are electrically connected in series by viaconductors 756 extending through the structure 750, so as to form asolenoid in the form of a flattened helix. Each turn of the helix isconstituted by a first conductor 752, a via conductor 756, a secondconductor 754 and another via conductor 756 at the opposite end of suchsecond conductor, which in turn connects to a first conductor 752constituting part of the next turn.

As best seen in FIG. 14, the generally planar or sheet-like structure750 may include an internal metallic layer 780, a first dielectric layer782 on one side of the metallic layer and a second dielectric layer 784on the opposite side of the metallic layer. The dielectric layers may beformed, for example, by coating a dielectric material onto the metalliclayer. For example, the dielectric layers 782 and 784 may be formed byelectrophoretic deposition on the metallic layer. These dielectriclayers may be continuous with a dielectric coating 786 extending throughholes in the metallic layer. One particularly desirable process forforming such a structure is disclosed in co-pending, commonly-assignedU.S. patent application Ser. No. 09/119,079, filed Jul. 10, 1998, thedisclosure of which is hereby incorporated by reference herein. As bestappreciated with reference to FIG. 14, the turns of the helical inductorwill encompass a section 790 of the metallic layer. That section 790 maybe formed from a ferromagnetic material. The remaining sections of themetallic layer may be formed from a non-ferromagnetic material.Alternatively, the metallic layer may be omitted entirely. In analternative arrangement, the ferromagnetic core of the inductor may beprovided as a discrete ferromagnetic element which is not part of alarger metallic layer. Such a discrete ferromagnetic element may beembedded within the dielectric structure.

In the embodiment depicted in FIG. 13, the solenoid extends along astraight path. As depicted in FIG. 15, a similar solenoid may beprovided in a curved or toroidal structure extending along all or partof a loop-like path 792.

An inductor according to a further embodiment of the invention (FIGS. 16and 17) includes a first or interior solenoid 802 formed by first sideconductors 804 on a first side 806 of a substrate 808 incorporating adielectric layer and by first loop conductors in the form of wire bonds810 connected between conductors 804. The first loop conductors or wirebonds 810 project upwardly from the first surface 806 of substrate 808.Each such first loop conductor or wire bond extends from an end of onefirst side conductor 804 to the opposite end of another first sideconductor 804. Each turn of interior solenoid 802 includes one firstside conductor 804 and one first loop conductor or wire bond 810. Asecond or outer solenoid 812 is formed by second side conductors 814 onthe second, opposite side 816 of the substrate 808. Bond windows 818 areprovided in alignment with pads 820 at the ends of the second sideconductors. Second loop conductors or wire bonds 822 extend from pads820 through the bond windows 818 to the first surface and extendupwardly away from the first surface 806 of the substrate. The secondloop conductors or wire bonds 822 and second side conductors 814 areconnected in series with one another to form the outer solenoid 812.Each turn of the outer solenoid includes one second conductor 814 andone second loop conductor or wire bond 822. The inner and outersolenoids are concentric with one another. Inner solenoid 802 issurrounded by outer solenoid 812. A structure as depicted in FIGS. 16and 17 may be used to provide a high-value inductor (where the inner andouter solenoids are electrically connected in series) or a transformer(where the inner and outer solenoids are not electrically connected toone another). This structure also can be made in a toroidalconfiguration.

A component usable in a further embodiment of the invention is depictedin fragmentary view in FIG. 18. The component according to thisembodiment includes a substrate 850 incorporating a dielectric layer.The substrate desirably is generally planar or sheet-like. A pluralityof conductive elements 852 are arrayed along a path 854. The substratehas bond windows 856 and 858 disposed on opposite sides of path 854.Each conductive element includes a first lead portion 860 aligned withbond window 856 on one side of the path, a second lead portion 862aligned with the bond window 858 on the opposite side of path 854 and atrace portion 864 extending along the substrate between the leadportions. The ends of the lead portions remote from path 854 and remotefrom the trace portions 864 optionally may be connected to anchors 866,868 by frangible portions 870, 872 as depicted in FIG. 18.

To form the indictor, the component is assembled with a chip, substrateor other element 880 (FIG. 19) having an array of conductors 882arranged along a similar path 884. Conductors 882 are also elongated andextend generally transverse to path 884. Component 850 is juxtaposedwith component 880 so that path 854 overlies path 884 and extendsgenerally parallel thereto, and so that the bond windows 858 and 856overlie the ends of conductors 882. The first lead portion of 860 ofeach conductive element on component 850 is bonded to one end of aconductor 882, whereas the second lead portion 862 is bonded to theopposite end of the next adjacent conductor 882 on the chip or othermating element 880. The connected conductive elements 852 and conductors882 form a solenoid. Each turn of the solenoid includes a conductor 882on element 880; a first lead portion projecting away from element 880and towards the substrate 850; the trace portion 864 of the sameconductive element and the second lead portion 862 extending downwardlytoward 880, where it joins the conductor 882 constituting the next turn.Such an inductor can provide a relatively large cross-sectional areawithin each turn in a compact structure. Moreover, such an inductor canbe formed by the same lead bonding techniques used to fabricate otherconnections in the packaged chip or module. A ferromagnetic core can beprovided in such an inductor by providing a strip of ferromagneticmaterial in the substrate 850 or by mounting a strip of ferromagneticmaterial on the inner surface of substrate 850 (facing towards matingelement 880) or on the surface of mating element 880. In a particularlypreferred arrangement, such an inductor can be provided by providing theconductive elements 852 on the chip carrier and bonding the leadportions of the conductive elements to a passive chip or active chip,during fabrication of a packaged module. In this case, the conductors882 can be thin-film components or, more preferably, can be thick-filmelements applied on the surface of the chip.

A module in accordance with a further embodiment of the invention (FIG.21) is generally similar to the module depicted in FIG. 8. However, thechip carrier or substrate 918 in this arrangement incorporates a“two-metal” structure, with terminals 922 on the outer or bottom surfaceand with terminal leads 926 projecting through bond windows or openingsin the chip carrier to the chips. A metallic structure is also providedon the inner surface 938 of the chip carrier. Each of the active chips914 and 906 in this embodiment is a surface acoustic wave chip. As bestseen in FIG. 22, chip 914 has a front surface 935 with an acoustictransmission region 902. Internal elements 904 and 906 are arranged totransmit and receive acoustic waves along the surface of the chip withinregion 902. Various surface acoustic wave devices are well known in theart. These include filters for selecting a signal of a particularfrequency and convolvers arranged to combine multiple signals with oneanother. It is important to keep surface region 902 free of otherattached structures and encapsulants in the packaged device.

Chip carrier 918 has a hole 901 extending into the chip carrier from theinner surface 950. A metallic ring 911 is formed on the inner surfaceand surrounds hole 901. The metallic ring may be formed integrally withother metallic features on the inner surface, or may be separatetherefrom. During manufacture, the front face 935 of chip 914 isjuxtaposed with the inner surface of the chip carrier and is bonded tothe chip carrier at ring 911. Thus, hole 901 provides a gas-filledcavity in alignment with the active surface region 902. The substratedoes not contact the active surface region 902. A bonding material 903desirably is provided between the inner surface of the chip carrier andthe front face 935 of chip 914. For example, the bonding material may bea so-called “dry pad,” i.e., a pre-formed pad of a die attach material.The die attach material 903 is provided with a pre-formed hole prior toplacing the die attach material between the front face of the chip andthe chip carrier extending entirely around hole 901. The die attachmaterial forms a seal between the front face of the chip and the innersurface of the chip carrier. During a subsequent stage of manufacture,encapsulant 917 is applied. The seal between the front face 935 of thechip and the inner surface of the chip carrier prevents entry of theencapsulant into hole 901. Alternatively or additionally, if chip 914 isprovided with a ring-shaped metallic bond pad on its front face, thebond pad may be metallurgically bonded to ring 911 so as to form asimilar seal extending entirely around hole 901 and active surfaceregion 902.

Hole 901 desirably is closed or “blind,” so that the hole does notcommunicate with the bottom or outer surface 942 of the substrate. Hole901 may be formed by any suitable technique used to for making blindvias in dielectric substrates. Desirably, hole 901 is partially filledwith a metallic material. Thus, the hole 901 may have metallic via liner907 extending along the wall of the hole. The via liner may join with ametallic element 909 on the outer or bottom surface of the substrate.This metallic element serves to close the hole. Moreover, metallicelement 909 can be bonded by a solder mass 909, or other metallurgicalbonding element, to a contact pad on the circuit panel. The via liner907 thus serves as a heat-conducting element, so as to abstract heatfrom chip 914. In a variant of this structure, the chip carrier orsubstrate 918 is a “single metal” construction, with metallic featureson only the outer or bottom surface 942, and hence ring 911 is omittedand hole 901 does not have a via liner. In a further variant, thesubstrate is a single-metal design with metallic features on only theinner or upper surface 950. The hole 901 in the dielectric of thesubstrate may be omitted, if ring 911 has sufficient thickness tomaintain the active surface region 902 of chip 914 out of contact withthe inner surface of the substrate. Alternatively, a hole may be formedpartially or completely through the substrate within ring 911 to provideadditional clearance. If the hole extends completely through thesubstrate, it may be closed by an additional element as, for example, asolder mask layer or other sheetlike structure applied on the bottom orouter surface of the substrate.

Structures according to this arrangement provide a gas-filled space incontact with the acoustic region of the surface acoustic wave chip, butalso provide the other advantages achieved by mounting a chip in apackage having a relatively thin chip carrier. Thus, the entire assemblycan be substantially as compact as a unit which does not incorporate asurface acoustic wave device. Moreover, the structure is compatible fromthe manufacturing techniques used to make packaged chips and modulesaccording to other embodiments of the invention, and the resultingpackaged chip can be handled and mounted in the same manner as any othersurface-mountable device. In the embodiments of FIG. 21, the surfaceacoustic wave chip is provided as part of a circuit or assemblage with apassive chip 915, and the module includes a similar assemblage withanother surface acoustic wave chip 954 and passive chip 956. However,features such as the hole 901 and bonding material 903 can be used inpackages which include only a single surface acoustic wave chip.

A packaged chip assembly according to yet another embodiment of theinvention (FIG. 23) incorporates a chip carrier 1018 similar to the chipcarriers discussed above and also has an enclosure 1070 similar to thosediscussed above. First or active chip 1014 is mounted on the thermalconductor 1020 of the chip carrier, with the front or contact-bearingsurface 1035 of the active chip facing upwardly, away from the chipcarrier and thermal conductor, and with the rear surface 1044 of theactive chip facing downwardly, toward the thermal conductor. A passiveor second chip 1015 is mounted over the active chip 1014 so that thecontact-bearing surface 1017 of this chip confronts the contact-bearingsurface 1035 of the active chip. Contacts 1019 of the passive chip 1015are bonded to contacts 1034 of the active chip as, for example, by smallsolder bonds, diffusion bonding or other metallurgical bondingtechnique. Alternatively, other interconnection techniques such as asilver-filled epoxy or other metal and polymer composite, or a layer ofanisotropic conductive material may be provided between these chips soas to interconnect mutually facing contacts on the two chips. Acomposite material of the type sold under the trademark ORMET may beemployed. Such a material includes a dielectric such as an epoxy, metalparticles and a solder, and cures to form continuous conductors formedfrom the metal particles and solder extending through the dielectric.

The second or passive chip projects outwardly in horizontal directionsgenerally parallel to the plane of chip carrier 1018 beyond the edges1021 of the active chip. The passive chip has outer contacts 1023disposed beyond the edges of the active chip, and has conductors 1025connected to these outer contacts. Conductors 1025 may connect directlywith contacts 1019 and, hence, directly with contacts 1035 of the activechip. The passive chip also incorporates passive components, desirablyresistors and capacitors, symbolized by a resistor 1027. As will beappreciated, a number of passive components may be incorporated withinthe passive chip. Also, some or all of the outer contacts 1023 of thepassive chip may be connected to or through such passive components. Ifthe package includes additional discrete components (not shown) oradditional chips (not shown), the connections between outer contacts1023 and inner contacts 1019 may include these elements.

The front, contact-bearing surface 1017 of the passive chip facesdownwardly, toward the chip carrier or substrate 1018. Thus, the outercontacts 1023 of the passive chip may be readily connected to theterminals 1022 of the chip carrier by leads 1026 similar to thosediscussed above. Moreover, because the rear surface 1044 of the activechip confronts the thermal conductor 1020, the rear surface of theactive chip may be closely coupled to the thermal conductor so as toprovide excellent heat transfer from the active chip to the thermalconductor and through the thermal conductor to the circuit panel. Forexample, the rear surface of the active chip may be coupled by a layerof solder or other metallic bonding material to the thermal conductor.The rear surface 1044 of the active die may be provided with recesses1004 and rear surface contacts 1002 similar to the rear surface contacts202 and recesses 204 discussed above with reference to FIG. 4. Hereagain, the rear surface contacts may serve as ground or powerconnections to the active die, and provide additional thermalconductivity 1020. As discussed above, the thermal conductor itselfdesirably is coupled to the thermal conductor mounting pad of thecircuit panel by a large mass of solder or other metallic bondingmaterial 1052. Additionally, the passive chip is coupled to enclosure1070, as by a thin layer of die-bonding material or encapsulant havinghigh heat conductivity, so that both the passive chip and the activechip can be cooled by heat transfer to enclosure 1070. Here again,inductors can be provided in the chip carrier itself or by structuressuch as those discussed above, including portions formed in the chipcarrier and portions extending between the chip carrier and the passivechip.

An assembly according to yet another embodiment of the invention (FIG.24) includes an active chip 1114 and a passive chip 1115 as discussedabove with reference to FIG. 23. In this embodiment, however, theorientation of the chips is reversed. Thus, active chip 1114 is mountedabove the passive chip 1115, and the front or contact-bearing surface1135 of the active chip faces downwardly, toward the chip carrier 1118.The front surface 1117 of the passive chip 1115 faces upwardly, awayfrom the chip carrier. The outer contacts 1123 of the passive chip areconnected by leads in the form of wire bonds to terminals 1122 on thechip carrier. The rear surface of the active chip is in thermalcommunication with the top wall structure 1171 of the spreader orenclosure 1170, whereas the rear surface of the passive chip is inthermal communication with a thermal conductor 1120, which is bonded toa mating metallic element 1152 on the circuit board 1112 when theassembly is mounted on a circuit board. Thus, the passive chip 1115 andthermal conductor provide a thermal path between the active chip and thecircuit board when the module is mounted to the circuit board. Moreover,the spreader or enclosure 1170 provides further thermal dissipation fromthe active chip to the surroundings.

In the embodiment of FIG. 24, the side wall structure 1172 of theenclosure terminates just above the top or inner surface of chip carrier1118. A flange 1174 at the bottom of the side wall structure is bondedto a metallic rim structure 1177 on the chip carrier, as by a solder orother metallic bonding material 1175 during manufacture of the module.Rim structure 1177 may be in the form of a continuous ring or a seriesof pads extending around the periphery of the chip carrier. The rimstructure is exposed at the bottom or outer surface of the chip carrier,as by an opening or series of openings 1179 extending through the chipcarrier. When the module is mounted to circuit board 1112, the rimstructure is bonded to a mating element or set of elements 1181 on thecircuit board, to provide a good heat dissipation path between enclosure1170 and the board. This connection, as well as the connection of thethermal conductor 1120 to the board, can be accomplished in the samesurface mounting operation used to connect terminals 1122 to the matingcontacts on the circuit board. Moreover, element 1181 can be provide aground connection to the enclosure. The embodiment of FIG. 24 uses a“circuits-in” configuration, with the metallic features of the chipcarrier disposed on the inner or upper surface 1101. Similar structurescan be provided in a “circuits-out” arrangement, with the metallicfeatures on the lower or bottom surface 1103. In a further variant, thepassive chip 1115 may have a conductive rear surface forming a commonconnection such as a ground or power connection, or may be provided withground or power contacts (not shown) at discrete locations on the rearsurface or in recesses open to the rear surface, similar to the rearsurface contacts discussed above with reference to FIGS. 4 and 23.

A technique for making numerous packages incorporating spreaders orenclosures uses a substrate 1200 (FIG. 25) in the form of a continuousor semi-continuous sheet or tape having numerous regions 1202, eachincluding the features needed to form a single package such as a packageaccording to any of the embodiments discussed above. For example, eachregion 1202 may incorporate a thermal conductor or bottom shield 1204,leads 1206 (of which only a few are shown in FIG. 25), as well asterminals 1205 (FIG. 27). Each region desirably also includes bondwindows 1208. In the unassembled state shown in FIG. 25, leads 1206extend across the bond windows. Thus, each region may include astructure similar to the structure discussed above with reference toFIG. 2, or any of the other variants of such a structure needed to formthe other packages described above. Tape 1200 also has a large number ofenclosure openings 1212 spaced apart from one another and arranged inrows such that each region 1202 of the tape is substantially surroundedby rows of enclosure openings and such that rows of enclosure openings1212 form borders between adjacent regions. The process also uses a topsheet 1214 desirably a conductive sheet such as a metallic sheet havingrows of projections 1216 extending from one surface of the sheet.Projections 1216 are arranged with spaces 1217 between them. Theprojections are disposed in locations corresponding to the locations ofenclosure openings 1212 and are arranged in rows corresponding to therows of enclosure openings so that the projections 1216 subdivide sheet1214 into numerous regions 1218.

In the assembly method, the conductive sheet 1214 is assembled with thesubstrate sheet 1200 so that each region 1218 of the conductive sheetoverlies one region 1202 of the substrate sheet, and so that theprojections 1216 on the conductive sheet are aligned with enclosureopenings 1212 of the substrate sheet. In the assembled condition, theprojections 1216 extend from sheet 1214 to substrate 1200, leaving a gapor space between the sheet and the substrate. In the particularembodiment depicted, each projection 1216 extends through one enclosureopening 1212 and extends slightly below the bottom or outer surface ofsheet 1200.

The chips and other elements to be incorporated in the packages areassembled to the sheets so that the elements to be incorporated in eachpackage are disposed between a region of conductive sheet 1214 and thecorresponding region of substrate sheet 1200. In the embodiment depictedin FIG. 27, each package includes a single chip 1220, but the assemblymethod is applicable regardless of whether each package is to includeone chip or a plurality of chips or other components. Assembly of theinternal components may be performed by assembling the internalcomponents to the conductive sheet, to the substrate sheet, or both,before the conductive sheet is assembled with the substrate sheet. Forexample, chip 1220 may be assembled to substrate sheet 1200 andtemporarily supported on small elements or “nubbins” 1222, as discussedabove. Alternatively, chip 1220 may be mounted on the inner surface ofsheet 1214 (the surface facing toward substrate sheet 1200 in theassembled condition) so that the chip will be in the desired positionwhen the conductive sheet is assembled to the substrate sheet. Chip 1220is connected with the leads 1206 for terminals 1205 and for thermalconductor 1204 in the manner described above. In the embodimentillustrated, these connections are made using bond windows 1208, but theparticular connections and manner of connecting will vary with the typeof internal component employed. The connecting step also may beperformed before or after the substrate sheet is united with theconductive sheet.

Where the substrate sheet 1200 incorporates bond windows 1208 or otheropenings apart from the enclosure openings 1212, a cover layer 1224 isapplied on the outer or bottom surface of the substrate sheet so as toclose the bond windows after making the connections with leads 1206. Inthe next stage of the process, an encapsulant is injected between thesubstrate sheet and the conductive sheet. The encapsulant may beinjected at one or more edges of the sheets or at one or more pointsalong the extent of the sheets. Because projections 1216 are spacedapart from one another, they do not form continuous barriers and,accordingly, encapsulant can flow to all of the various regions 1202 ofthe substrate sheet. Thus, as schematically indicated by arrows 1228 inFIG. 27, the encapsulant flows between the various regions through thespaces 1217 (FIG. 26) between the projections 1216. During this phase ofthe process, the sheets may be held between fixtures. Alternatively oradditionally, the sheets may be held in frames. As described in greaterdetail in U.S. Pat. Nos. 6,329,224 and 6,133,639, the disclosures ofwhich are hereby incorporated by reference herein, the injection stepmay be performed at a production station and the assembled sheets, withthe injected encapsulant, may be removed from such production stationand subjected to a curing process in an oven or at another locationseparate from the injection station. Some or all of the fixtures used tohold the sheets may be advanced from the injection station to the curingoperation along with the assembled sheets. These elements may bedisposable or other elements which can be provided in large quantities,so that numerous assemblies can be cured simultaneously.

After curing of the encapsulant, the sheets are severed as by cuttingalong cutting planes 1230 extending between adjacent regions 1202 of thesubstrate sheet and adjacent regions 1218 of the conductive sheet. Thesevering operation yields numerous units 1232 (FIG. 28). Each unitincludes one region 1202 of the substrate sheet and the associated chipsor other microelectronic components. Each such unit includes anenclosure or spreader having an upper or rear wall formed by one region1218 of the conductive sheet and having side walls constituted byspaced-apart portions 1234 of the projections which were present on theconductive sheet. The side walls in this instance project downwardlybeyond the substrate or chip carrier 1202. As discussed above, each suchunit can be mounted to a circuit board with the bottom edges 1236 of theside walls being bonded to spreader connection pads on the circuitboard.

The side walls formed by spaced-apart portions 1234 have gaps 1236corresponding to the spaces 1217 (FIG. 26) between projections 1216.Nonetheless, the side walls can provide effective electromagneticshielding, provided that the gaps are small enough in relation to thewave lengths of the electronic signals which must be confined within theunit or excluded from the unit. Desirably, the gaps 1236 have a maximumdimension less than the wavelength of the signals to be processed in theunit. In a typical example, the projections on the conductive sheet havedimensions of a few millimeters or less, typically about 1 millimeter,and the gaps 1236 likewise have dimensions of a few millimeters,typically about 1 millimeter or smaller.

In the embodiments discussed with reference to FIGS. 25-28, theprojections 1216 extend entirely through the substrate. However, this isnot essential. In an alternate embodiment, the projections may extenddownwardly into proximity with the substrate but do not extend throughthe substrate. For example, the substrate may be provided with spreadermounting elements on its top or inner surface, similar to the spreadermounting elements or rim structure 1177 shown in FIG. 24. Theprojections of the conductive sheet may be bonded to these spreadermounting elements when the conductive sheet is assembled to thesubstrate sheet. Also, in the embodiments discussed above with referenceto FIGS. 25-28, each region 1202 of the substrate is associated with allof the internal components to be incorporated in a single package, andeach unit produced by the severing operation includes only one region ofthe substrate sheet. In further embodiments, the severing operation maybe varied so as to produce larger units or modules each incorporatingtwo or more regions of the substrate sheet and the chips or otherelectronic elements associated with both regions of the substrate sheet.In such an arrangement, each module produced by the severing operationwill include one or more rows of metallic projections 1216 disposedbetween adjacent regions 1202 of the substrate sheet. These projectionsform a medial wall structure isolating the various regions of thecompleted module from one another in a manner similar to the medial wallstructures 675 discussed above with reference to FIG. 8. Also, theassembly and encapsulation methods discussed above can be employed topackage microelectronic elements other than semiconductor chips orassemblies including semiconductor chips.

As illustrated in FIG. 29, the inductor-forming arrangement discussedabove with reference to FIGS. 18-20 can be modified so as to formconcentric inductors. As in the embodiment of FIG. 18, the componentincludes a substrate 1350 incorporating a planar or sheetlike element.Here again, the substrate may be the chip carrier used in a packagedsemiconductor chip or module. A first set of conductive elements 1352 isarrayed along a path 1354 similar to the path 854 discussed above withreference to FIG. 18. Path 1354 extends into and out of the plane of thedrawing in FIG. 29. Here again, each first set conductive element 1352includes a first lead portion 1360 aligned with a bond window 1356 onone side of the path and a second lead portion 1362 disposed on theopposite side of path 1354 and aligned with a second bond window 1358 inthe substrate, and a trace portion connecting the first and second leadportions 1360 and 1362. The component also includes a second set ofconductive elements 1353 disposed on the opposite side of substrate1350, i.e., on the upwardly-facing side in FIG. 29. Each such second-setconductive element also includes a trace portion, a first lead portion1361 aligned with the first bond window 1356 on one side of the path anda second lead portion 1363 aligned with the second bond window 1358 onthe opposite side of the path. In the embodiment illustrated, the firstand second sets of conductive elements are aligned with one another, sothat each first lead portion 1360 of the first set extends beneath afirst lead portion 1361 of the second set and each second lead portion1362 of the first set extends beneath a second lead portion 1363 of thesecond set. Each pair of first lead portions 1360 and 1361 is separatedfrom one another by a strip 1302 of dielectric material formedintegrally with substrate 1350 projecting partially across the bondwindow. The aligned first lead portions and strip 1302, thus, form acomposite, multiconductor lead 1306. The structure of suchmulticonductor lead may be identical to the multiconductor leadstructures described in U.S. Pat. Nos. 6,329,607 and 6,239,384, thedisclosures of which are hereby incorporated by reference herein.Likewise, each pair of aligned second lead portions 1362 and 1363 isprovided with a similar strip of dielectric material 1304 to form afurther composite multiconductor lead 1308 on the opposite side of path1354.

The mating element 1380 used with this component is provided with twoarrays of conductors 1382 and 1383, each such array also being arrayedalong a similar path 1384. The conductors 1382 of the first setdesirably are electrically insulated from adjacent conductors 1383 ofthe second set. Here again, the conductors 1382 and 1383 are generallyelongated and extend generally transverse to path 1384.

In a manner similar to the assembly operation discussed with referenceto FIGS. 18-20, the component incorporating substrate 1350 is assembledto the mating element 1380 so that path 1354 overlies path 1384 andextends generally parallel thereto, and so that the bond windows 1356and 1358 overlie the ends of the conductors 1382 and 1383.

As in the embodiment discussed above with reference to FIGS. 18-20, thefirst lead portion 1360 of each first-set conductive element on thecomponent 1350 is aligned with one end of a conductor 1382 of the firstset on component 1382, whereas the second lead portion 1362 is alignedwith the opposite end of the next adjacent conductor 1382. Similarly,the first lead portion 1361 of each second-set conductive element isaligned with one end of a conductor 1383, whereas the second leadportion 1363 or each second-set conductive element is aligned with theopposite end of an adjacent conductor 1383. The aligned lead ends andconductor ends are bonded to one another. The procedures used forbonding ends of the multiconductor leads 1306 and 1308 can be asdescribed in the aforementioned '607 and '384 patents. The resultingstructure yields a pair of misted solenoids, one such solenoid beingformed from the conductors 1382 of the first array and the conductiveelements of the first set, the other such solenoid being formed from theconductors 1383 and the conductive elements of the second set.

In the embodiment discussed above with reference to FIG. 29, the numberof second lead portions is equal to the number of first lead portionsand, hence, the number of turns in each solenoid is the same. However,this is not essential. Thus, if some of the first lead portions areomitted or are not connected in the inner solenoid, the inner solenoidwill have fewer turns than the outer solenoid. Likewise, if some of thesecond lead portions are omitted or not connected, the outer solenoidwill have fewer turns.

In a further variant (FIG. 30), the first-set conductive elements 1452again extend on one surface of substrate 1450, whereas the second-setconductive elements 1453 extend on the opposite surface, but the leadportions of the first and second set are offset from one another in thedirection along the length of the path 1454. Thus, first lead portions1460 of the first set are interspersed in the lengthwise direction ofthe path with the first lead portions 1461 at one bond window, whereasthe second lead portions 1462 of the first set are interspersed with thesecond lead portions 1463 of the second set at the opposite bond window.The various lead portions may be connected to a mating element such as achip or other element similar to the element 1380 discussed above,having two separate sets of conductors. This arrangement will alsoprovide concentric solenoids, one including the conductors of the firstset and the other including the conductors of the second set. As in theother inductor embodiments discussed above, the paths 1354 (FIG. 29) and1454 (FIG. 30) may be either straight or curved and may be close curvesso as to form concentric toroidal solenoids.

As these and other variations and combinations of the features set forthabove can be utilized, the foregoing description of the preferredembodiment should be taken by way of illustration rather than bylimitation of the invention.

1. A packaged semiconductor chip comprising: (a) a first semiconductorchip having an upwardly-facing front face, a downwardly-facing rearface, edges bounding said faces and contacts exposed at said front face,said first semiconductor chip including active components; (b) aconnecting element including passive components, said connecting elementbeing electrically connected to at least some of said contacts, saidconnecting element overlying said front face of said first chip andprojecting outwardly beyond said edges of said first chip; (c) a chipcarrier disposed below said rear face of said first chip, said chipcarrier having a bottom surface facing downwardly away from said firstchip and having a plurality of terminals exposed at said bottom surface,at least some of said terminals being electrically connected to at leastsome of said contacts of said first chip through said connectingelement; and (d) deformable leads connecting said terminals to saidconnecting element.
 2. A packaged semiconductor chip comprising: (a) afirst semiconductor chip having an upwardly-facing front face, adownwardly-facing rear face, edges bounding said faces and contactsexposed at said front face, said first semiconductor chip includingactive components; (b) a connecting element including passivecomponents, said connecting element being electrically connected to atleast some of said contacts, said connecting element overlying saidfront face of said first chip and projecting outwardly beyond said edgesof said first chip; (c) a chip carrier disposed below said rear face ofsaid first chip, said chip carrier having a bottom surface facingdownwardly away from said first chip and having a plurality of terminalsexposed at said bottom surface, at least some of said terminals beingelectrically connected to at least some of said contacts of said firstchip through said connecting element, wherein said chip carrier includesa dielectric element having an exposed surface defining said bottomsurface of said chip carrier and said terminals are exposed at saidbottom surface within openings in said dielectric element; and (d)deformable leads connecting said terminals to said connecting element.3. A packaged semiconductor chip as claimed in claim 1 or 2, whereinsaid deformable leads are formed integrally with said terminals.
 4. Apackaged chip as claimed in claim 1 or 2 wherein said connecting elementprojects beyond said edges of said first chip.
 5. A packaged chip asclaimed in claim 1 or 2 further comprising a hollow can encompassingsaid first chip, said can having a top wall extending above said firstchip and having side walls extending downwardly from said top wall.
 6. Apackaged chip as claimed in claim 5 wherein said side walls of said canare attached to said chip carrier.
 7. A packaged chip as claimed inclaim 5 wherein said side walls of said can extend outside of theperiphery of said chip carrier.
 8. A packaged chip as claimed in claim 1or 2 wherein said first chip includes active semiconductor components.9. A packaged chip as claimed in claim 8 wherein said passive componentsin said connecting element include at least one passive componentselected from the group consisting of resistors and capacitors.
 10. Apackaged chip as claimed in claim 9 further comprising at least oneinductor formed at least in part on said chip carrier.
 11. A packagedchip as claimed in claim 1 or 2 further comprising an electricallyconductive enclosure element overlying said connecting element.
 12. Apackaged chip as claimed in claim 11 wherein said enclosure element is ahollow can having a rear wall overlying said connecting element andhaving side walls extending downwardly to the vicinity of said chipcarrier.
 13. A packaged chip as claimed in claim 1 or 2 wherein saidchip carrier is a sheet-like element having thickness in the verticaldirection less than about 150 microns.
 14. A packaged chip as claimed inclaim 13 wherein said chip carrier includes a thermal conductorunderlying at least a major portion of said rear face of said firstchip, said thermal conductor being in thermal communication with saidfirst chip, said thermal conductor being exposed at said bottom surfaceof said chip carrier.
 15. A packaged chip as claimed in claim 14 whereinsaid thermal conductor and said terminals are adapted for surfacemounting to a circuit board.
 16. A packaged chip as claimed in claim 1or 2 wherein said chip carrier includes peripheral portions extendingoutwardly beyond the edges of said first semiconductor chip, all of saidterminals being disposed in said peripheral portions.
 17. A packagedchip as claimed in claim 1 or 2 wherein said connecting element is asecond semiconductor chip.
 18. A packaged chip as claimed in claim 17wherein said first semiconductor chip and said second semiconductor chipinclude different semiconductor materials.
 19. A packaged chip asclaimed in claim 17 wherein said second semiconductor chip has minimumfeature size larger than the minimum feature size of said firstsemiconductor chip.
 20. A packaged semiconductor chip as claimed inclaim 1 or 2 wherein said first semiconductor chip is a radio frequencypower amplification chip.
 21. A packaged semiconductor chip as claimedin claim 2, wherein contact surfaces of said terminals are separatedfrom said bottom surface of said chip carrier by said dielectricelement.